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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7127/VSC7129
Features
* ANSI X3T11 Fibre Channel Compliant * 1.0625Gb/s Operation * Features the FibreTimerTM Configurable Clock Recovery Unit (CRU): Repeater, Retimer or Bypassed * Six Port Bypass Circuits (PBC) *
Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel
Analog/Digital Signal Detect (SDU)
* On-Chip Transmit Termination * 3.3V, 700mW Power Dissipation
* Compatible with HDMP-0451 (VSC7127) or HDMP-0452 (VSC7129) * 44-Pin, 10mm PQFP Package
General Description
The VSC7127 and VSC7129 contain six cascaded Port Bypass Circuits (PBCs), the FibreTimerTM configurable Repeater/Retimer (CRU) and a Signal Detect Unit (SDU). These parts are typically used in distributing Fibre Channel signals to an array of disk drives in an FC-AL loop as illustrated in Figure 1. The first VSC7127's CRU is configured as a Repeater to attenuate jitter, the second VSC7127's CRU is bypassed to reduce power and the third VSC7127's CRU is configured as a retimer so that the output of the device is a jittercompliance point. Each PBC is a multiplexer that is controlled by the corresponding SELx line which, if HIGH, selects the external input or, if LOW, selects the output of the previous PBC. For the VSC712xR, when MODE is LOW and SEL5 is HIGH, the CRU is a sophisticated repeater which has low latency, no peaking and attenuates jitter even at low frequencies. When MODE is HIGH and SEL5 is HIGH, the CRU is a retimer which eliminates jitter transfer but has increased latency due to an elasticity buffer which adds/drops Fibre Channel fill words in order to accomodate the difference between the baud rate of the incoming data and the local REFCLK. When SEL5 is LOW, the CRU is bypassed and powered down. The SDU monitors the analog levels of the IO+/- input and monitors the output of the CRU digitally to indicate whether valid data is present. The VSC7127/VSC7129 are similar to the VSC7124 which does not contain the FibreTimerTM cell or CMU.
VSC7127/VSC7129 Block Diagram
O1+ O1I1+ I1SEL1 O2+ O2I2+ I2SEL2 O3+ O3I3+ I3SEL3 O4+ O4I4+ I4SEL4 O0+ O0I0+ I0SEL0 1 0
REFCLK 106.25MHz
CMU
1 0 1 0 1 0 1 0
0.1uF
PBC1
SEL5 1 0
PBC2
PBC3
PBC4
PBC0
PBC5 CRU
MODE
SDU
SIGDET
G52298-0, Rev 4.3 05/01/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel
Data Sheet
VSC7127/VSC7129
Application: Fibre Channel Disk Arrays
A 12-port JBOD is shown in Figure 1. This dual loop application uses 3 VSC7127Xs on each loop in order to configure the FC-AL disk array. Functional drives are included in the FC-AL loop while non-functional or missing drives (numbers 2, 7, 9) are excluded.
Figure 1: 12-Drive FC-AL JBOD Application
Optics or Copper
1
LOOP A
Retimer
0 1
Retimer
0 1 0
VSC7127T #6
7125 SerDes 7125 SerDes
1
VSC7127T #5
0
1
2
7125 SerDes 7125 SerDes 7125 SerDes 7125 SerDes 7125 SerDes 7125 SerDes 7125 SerDes 7125 SerDes
0
1
4
VSC7121 QUAD PORT BYPASS CIRCUIT
0
1
3 4
0
1
3 0 1
VSC7127R #4
CONFIGURATION: 7127R #1 & 2: Repeater Mode SEL0=1, SEL5=1 MODE=0 7127R #3 & 4: Bypass Mode SEL5=0 MODE=x, No REFCLK 7127T #5 & 6: Retimer Mode SEL1=1, SEL5=1 MODE=1
0
1 1 0
2
0 4
1
5 6
0
1
VSC7127 R#3
0
1
0
1
3
0
1
7
7125 SerDes 7125 SerDes
0
1
2 0 1
8
0
1 0 0
1
0
1
9
0
1
4 0 1
VSC7127R #2
0
1
3
VSC7127R #1
0
1
0
1
2
0
1
Optics or Copper
0
1
1
7125 SerDes 7125 SerDes 7125 SerDes 7125 SerDes 7125 SerDes 7125 SerDes
10 11 12
LOOP B
Repeater
0
Repeater
Page 2
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52298-0, Rev 4.3 05/01/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7127/VSC7129
Functionality
Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel
Device Configurations Four devices are specified in this datasheet: VSC7127R, VSC7127T, VSC7129R and VSC7129T. The VSC7127 is pin-compatible to the HDMP-0451. The VSC7129 is pin compatible with the HDMP-0452. The VSC712xR is configured as a Repeater when pin 12, MODE, is LOW, or a Retimer when HIGH. The VSC712xT is configured as a Retimer when pin 12, MODE, is LOW, or a Repeater when HIGH. Port Bypass Circuits The VSC712x contains six Port Bypass Circuits (PBCs) which are 2-to-1 multiplexers used to steer serial signals. Each PBC, PBCx has a single select line, SELx, which when HIGH, selects the external input, Ix, to PBCx and when LOW, selects the output of the previous PBC. PCB5 does not have an external input but selects between the output of the CRU (when SEL5 is HIGH) and the output of PBC0 (when SEL5 is LOW). These controls allow FC-AL loops to include a functional device on the loop or exclude a non-functional device from the loop. FibreTimerTM Clock Recovery Unit--Repeater Mode The Clock Recovery Unit (CRU) is a digital PLL which extracts the clock from the incoming data and samples the data with the extracted clock. In repeater mode, the output of the CRU is synchronized to the recovered clock and has improved signal quality due to amplification of the signal and attenuation of jitter. Latency through the device is quite low, just a few bit times. Multiple repeaters can be cascaded without accumulation of jitter. MODE determines whether the CRU is a Repeater or a Retimer. FibreTimerTM Clock Recovery Unit --Retimer Mode MODE may configure the CRU as a retimer where the recovered data is placed into an elasticity buffer. Data is taken out of the elasticity buffer and retransmitted synchronously to the local REFCLK. For Fibre Channel data, Fill words will be added and dropped in the elasticity buffer in order to accomodate the differences in speed between the incoming data and the REFCLK. The retimer does not transfer jitter from the input to the output but has longer latency, up to 4 word times, through the device. FibreTimerTM Clock Recovery Unit--Bypass Mode When SEL5 is LOW, PBC5 selects the output of PBC0 and the CRU is unused. In this mode, the CRU is powered down to reduce power dissipation. If the part will be used only in this mode, REFCLK and MODE are ignored and can be left open. If the CRU is bypassed, the Signal Detect Unit is disabled and the output is LOW. Signal Detection A signal detect unit (SDU) monitors IO+/- and the output of the CRU to determine if there is a valid Fibre Channel signal present. The SIGDET is updated every 160 bits (an "interval") with the previous interval's status of three different Signal Detect Units: analog signal amplitude (ASDU), run length check (RLLSDU), Ordered Set density (OSSDU). If the input amplitude is less than 200mV (differential), ASDU will be set LOW. If the input amplitude is greater than 400mV, ASDU will be asserted HIGH. If a run length violation occurs (more than 5 consecutive ones or zeros), the RLLSDU will be set LOW and stay LOW until the occurrence of a valid
G52298-0, Rev 4.3 05/01/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel
Data Sheet
VSC7127/VSC7129
Fill Word or Primitive Sequence. Any Fill Word or Primitive Sequence will reset the OSSDU counter which will increment on any 160-bit sequence which is not a Fill Word or Primitive Sequence. If the counter reaches 256, a Fill Word or Primitive Sequence has not occured often enough so OSSDU is asserted until reset again. SIGDET is just an or'ing of these three state machines resynchronized to the 160-bit interval clock. If SEL5 is LOW or REFCLK is absent, the signal detect unit is disabled and SIGDET is LOW.
Application Example
Figure 2 shows one loop of an 8-drive JBOD implemented with two VSC712xs per loop. The input from the connector goes through a repeater in order to clean up the signal prior to the array of disk drives. After all eight PBCs, the output the to connector is retimed to ensure jitter compliance at the connector.
Figure 2: 8-Drive JBOD
Drive 2
O2 I2 1 0 SEL1 SEL2
Drive 3
O3 I3
Drive 5
O2 I2 SEL2 1 SEL3 0 SEL1 I1 O1 1 MODE SEL0 1
Drive 6
O3 I3
SEL3 O4
0
1
Drive 4
Drive 1
O4
1
I1 O1 0 MODE
MODE=0 SEL0=1
0 1
I4 SEL4
MODE=1 SEL1=1
0 1
I4 SEL4
RPTR
1 0 O0
RTMR
0 O0
1 SEL0 I0
I0
Drive 8
NOT SHOWN: PBC5, SEL5
Connector
Page 4
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Drive 7
G52298-0, Rev 4.3 05/01/01
0
1
1
0
1
0
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7127/VSC7129
Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel
AC Characteristics (Over Recommended Operating Conditions)
Figure 3: Timing Waveforms
Ix+/-
Ox+/T1 T1
Table 1: AC Characteristics (Over recommended operating conditions)
Parameters
T1 T1 TR, TF Tj(PBC) TJ(RPTR)
Description
Propagation delay (Repeater mode) Propagation delay (Retimer mode) Serial data rise and fall time Data jitter accumulation (PBC only) Total data output jitter (Repeater mode) Serial data output deterministic jitter (p-p) (Repeater mode) Total data output jitter (Retimer Mode)(1) Serial data output deterministic jitter (p-p) (Retimer Mode)(1) Jitter tolerance
Min
Typ
Max
7.0 180 300 120 192
Units
ns ns ps ps ps
Conditions
Delay with all circuits bypassed. Delay with all circuits bypassed. Typical delay is 100 bit times. At VIN minimum levels Peak-to-peak on Ox+/- in Port Bypass Circuit Mode. Jitter generation at Ox+/- when driven by the CRU in Repeater Mode. IEEE 802.3z Clause 38.68 Jitter generation at Ox+/- when driven by the CRU in Repeater Mode. IEEE 802.3z Clause 38.68 Jitter generation at Ox+/- when driven by the CRU in Retimer Mode. Jitter generation at Ox+/- when driven by the CRU in Retimer Mode. Minimum eye opening for proper operation as defined in MJS 8.0.
TDJ(RPTR)
80
ps
TJ(RTMR)
192
ps
TDJ(RTMR) TJTOL
80 0.24
ps UI
NOTE: (1) Retimer mode is only available for Fibre Channel applications.
G52298-0, Rev 4.3 05/01/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel
Data Sheet
VSC7127/VSC7129
Figure 4: REFCLK Timing Waveforms *
REFCLK
VIH(MIN) VIL(MAX)
NOTE: A reference clock must be provided to the REFCLK pin in order for the chip to power up in the right state.
Table 2: Reference Clock Requirements Parameters
FR FO DC TR, TF
Description
Frequency Range Frequency Offset Duty Cycle Rise and Fall Time
Min
105 -200 35
Typ
Max
107 200 65 2.0
Units
MHz ppm % ns
Conditions
Maximum frequency offset between transmit and receive reference clocks on one link Measured at 1.5V Between VIL(MAX) and VIH(MIN)
DC Characteristics (Over recommended operating conditions)
Parameters
VOH VOL VIH VIL IIH IIL VOUT75(1) VOUT50(1) VIN(1) VDD PD IDD IDDA
Description
Output HIGH voltage (TTL) Output LOW voltage (TTL) Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) TX output differential peak-topeak voltage swing TX output differential peak-topeak voltage swing Receiver differential peak-to-peak input Sensitivity RX Supply voltage Power dissipation Current (all supplies) Current (VDDA)
Min
2.4
Typ
Max
0.5
Units
V V V V A A mVp-p mVp-p mVp-p V mW mA mA
Conditions
IOH = -1.0mA IOL = +1.0mA
2.0 0 50
5.5 0.8 500 -500
VIN =2.4V VIN =0.5V 75 to VDD - 2.0 V 50 to VDD - 2.0 V Internally biased to VDD/2 3.3V5% Outputs open, VDD = VDD max. 2% Outputs open, VDD = VDD max VDDA = VDD max
1200 1000 400 3.14 707 215 50
2200 2200 2600 3.47 902 260 70
NOTE: (1) Refer to Application Note AN-37 for details regarding differential voltage measurements.
Page 6
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52298-0, Rev 4.3 05/01/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7127/VSC7129
Absolute Maximum Ratings (1)
Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel
TTL Power Supply Voltage (VDD)...................................................................................................... 0.5V to +4V PECL DC Input Voltage (VINP) ............................................................................................. -0.5V to VDD +0.5V TTL DC Input Voltage (VINT)........................................................................................................... -0.5V to 5.5V DC Voltage Applied to Outputs for High Output State (VIN TTL) ........................................ -0.5V to VDD + 0.5V TTL Output Current (IOUT), (DC, output high) .......................................................................................... +50mA PECL Output Current, (IOUT), (DC, output high)........................................................................................ -50mA Case Temperature Under Bias (TC).............................................................................................. -55oC to +125oC Storage Temperature (TSTG)........................................................................................................ -65oC to + 150oC Maximum Input ESD ................................................................................................................................... 1000V
Recommended Operating Conditions(2)
Power Supply Voltage (VDD) ....................................................................................................... +3.14V to 3.47V Ambient Operating Temperature Range (T)...............................................................0C Ambient to +95C Case
NOTES: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. (2) Vitesse guarantees the functional and parametric operation of the part under "Recommended Operating Conditions" except where specifically noted in the AC and DC Parametric tables.
G52298-0, Rev 4.3 05/01/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel
Data Sheet
VSC7127/VSC7129
Package Pin Descriptions
Figure 5: Pin Diagram
VDDP2 VDDP3 VSS O2+ O3+
O2-
O3-
I2+
I3+ 35
I2-
43 VSS VDD I1I1+ VDDP1 O1O1+ VSS I0I0+ VSS 11 13 9 7 5 3 1
41
39
37
I333
VSS VDDA
31
O4+ O4-
29
VSC7127 VSC7129
VDDP4 I4+
27
I4VDDP0
25
O0O0+
23 15 17 19 21
PIN23*
PIN20*
PIN21*
REFCLK
* See Tables 3 and 4 for Pin Differences and Description
Table 3: VSC7124/VSC7127/VSC7129 Pin Differences Pin 12
VSC7124 VSC7127 VSC7129 N/C MODE MODE
Pin 13
N/C REFCLK REFCLK
Pin 32
VDD VDDA VDDA
Pin 19
VSS VSS SIGDET
Pin 20
N/C SIGDET VDD
Pin 21
VDD VDD SEL5
PIN 19*
Pin 22
N/C SEL5 TRST
PIN22*
MODE
SEL1
SEL2
SEL0
SEL3
SEL4
Pin 23
N/C TRST VSS
Comment
Provided for reference only(1) Compatible with HDMP-0451 Compatible with HDMP-0452
NOTE: (1) The VSC7124 is a 5 PBC device similar to the VSC7127/VSC7129 without the FibreTimerTM Repeater/Retimer functionality.
Page 8
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52298-0, Rev 4.3 05/01/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7127/VSC7129
Table 4: Pin Identification Pin #
4, 3 41, 40 35, 34 28, 27 10, 9 15, 16, 17, 18 14, 22 7, 6 44, 43 38, 37 31, 30 24, 25
Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel
Name
I1+, I1I2+, I2I3+, I3I4+, I4I0+, I 0SEL1, SEL2 SEL3, SEL4 SEL0, SEL5 O1+, O1O2+, O2O3+, O3O4+, O4O0+, O0-
Description
INPUT - Differential, internally biased to VDD/2. I1+/I1- is the serial input to PBC1. I2+/I2- is the serial input to PBC2. I3+/I3- is the serial input to PBC3. I4+/I4- is the serial input to PBC4. I0+/I0- is the serial input to PBC0. INPUT - TTL. Port Bypass MUX SELect lines. A HIGH selects Ix. A LOW selects the output of the previous internal device. OUTPUT - Differential O1+/O1- is the serial output from O2+/O2- is the serial output from O3+/O3- is the serial output from O4+/O4- is the serial output from O0+/O0- is the serial output from MUX1. PBC port 1. PBC port 2. PBC port 3. PBC port 4.
13
REFCLK
INPUT - TTL 106.25MHz REFerence CLocK for the internal Clock Multiplier PLL. NOTE: A reference clock must be provided to the REFCLK pin in order for the chip to power up in the right state INPUT - TTL (NOTE: Different for VSC7127T or VSC7127R) In the VSC7127T, MODE configures the part as a Retimer if LOW or a Repeater if HIGH. In the VSC7127R, MODE configures the parts as a Repeater if LOW or a Retimer if HIGH. If unused, tie HIGH or LOW. OUTPUT - TTL: SIGnal DETect output INPUT - TTL: (Internal Pull-up Resistor) Test mode input. Pull HIGH or leave open for normal operation. Digital Logic Power Supply Power Supply (3.3V) for O1+/-. If unused, connect to VSS. Power Supply (3.3V) for O2+/-. If unused, connect to VSS. Power Supply (3.3V) for O3+/-. If unused, connect to VSS. Power Supply (3.3V) for O4+/-. If unused, connect to VSS. Power Supply (3.3V) for O0+/-. If unused, connect to VSS Analog Power Supply Ground
12 20 (VSC7127) 19 (VSC7129 23 (VSC7127) 22 (VSC7129) 2 21 (VSC7127) 20 (VSC7129) 5 42 36 29 26 32 1, 8, 11, 33, 39 19 (VSC7127) 23 (VSC7129)
MODE
SIGDET TRST VDD VDDP1 VDDP2 VDDP3 VDDP4 VDDP0 VDDA VSS
G52298-0, Rev 4.3 05/01/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 9
VITESSE
SEMICONDUCTOR CORPORATION
Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel
Data Sheet
VSC7127/VSC7129
Package Information
44-Pin PQFP 10 x 10 mm F G
44 34
Item
A D
mm
2.45 2.00 0.35 13.20 10.00 13.20 10.00 0.88 0.80
Tol.
MAX +0.10 +.05 +.25 +.10 +.25 +.10 +.15 / -.10 BASIC
1
33
E F G H I H I J K
11
23
12
12o TYP
22
D
12o TYP
K
0.30 RAD. TYP.
A
0.20 RAD. TYP. 0.25 MAX.
0.17 MAX. 0.25
NOTES: Drawing not to scale. Cavity up All units in mm unless otherwise noted.
0o- 8o
J1 E J
0.102 MAX. LEAD COPLANARITY
Page 10
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52298-0, Rev 4.3 05/01/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7127/VSC7129
Package Thermal Characteristics
Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel
The VSC7127/VSC7129 is packaged in a standard plastic quad flatpack, PQFP, with an embedded, but unexposed thermal heatslug. This package adheres to industry-standard EIAJ footprints for a 10 mm body, 44 lead PQFP. The package construction is as shown in Figure 6. The 44 PQFP with embedded slug has the thermal properties shown in Figure 6.
Figure 6: Package Cross Section--10 mm package
Plastic Molding Compound
Copper Heat Spreader
Lead
Bond Wire
Die
Table 5: 44 PQFP Thermal Resistance Symbol
CA-0 CA-100 CA-200 CA-400 CA-600
Description
Thermal resistance from case-to-ambient, still air Thermal resistance from case-to-ambient, 100 LFPM air Thermal resistance from case-to-ambient, 200 LFPM air Thermal resistance from case-to-ambient, 400 LFPM air Thermal resistance from case-to-ambient, 600 LFPM air
Value
50 43 39 36 34
Units
o o o o o
C/W C/W C/W C/W C/W
The VSC7127/VSC7129 is designed to operate with a case temperature up to 95oC. The user must guarantee that the case temperature specification is not violated. With the thermal resistances shown in Table 5, the 10mm PQFP can operate in still air ambient temperatures of 50oC [50oC = 95oC - 0.9W * 50]. If the ambient air temperature exceeds these limits, some form of cooling through a heatsink or an increase in airflow must be provided.
Moisture Sensitivity Level
This device is rated at a Moisture Sensitivity Level 3 rating with maximum floor life of 168 hours at 30C, 60% relative humidity. Please refer to Application Note AN-20 for appropriate handling procedures.
G52298-0, Rev 4.3 05/01/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 11
VITESSE
SEMICONDUCTOR CORPORATION
Family of Repeater/Retimer and Port Bypass Circuits for Fibre Channel
Data Sheet
VSC7127/VSC7129
Ordering Information
The order number for this product is formed by a combination of the device number and package type.
VSC712XX XX
Device Type VSC7127T Configured as a Retimer when MODE is HIGH. HDMP-0451 compatible VSC7127R Configured as a Repeater when MODE is LOW. HDMP-0451 compatible VSC7129T Configured as a Retimer when MODE is HIGH. HDMP-0452 compatible VSC7129R Configured as a Repeater when MODE is LOW. HDMP-0452 compatible Package Type QM: 44-pin PQFP, 10mm Body
Marking Information
The package is marked with three lines of text as shown in Figure 7 (VSC7127TQM shown).
Figure 7: Package Marking Information Pin 1 Identifier
VITESSE
Part Number DateCode
VSC7127T QM ####AAAAA
Package Suffix Lot Tracking Code (4 or 5 characters)
Notice
Vitesse Semiconductor Corporation ("Vitesse") provides this document for informational purposes only. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
Page 12
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52298-0, Rev 4.3 05/01/01

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